The present invention relates to methods and circuits for synchronizing multiple nodes transmitting on a bus in a multiplexed communication system, and more particularly to a method and circuit for managing the simultaneous, or near simultaneous, transmission and reception of a bit transition at a node by blocking transmission of bit transitions from the node for a predetermined period of time following reception of a bit transition.
With reference now to FIG. 1, a multiplexed communication system may include bus 10 for connecting plural nodes 12. The nodes 12 may include an interface circuit 14 for communicating on the bus 10, and a clocking element 16 for timing bit duration.
In multiple access communication systems two or more nodes 12 may be transmitting information on the bus 10 at the same, or nearly the same time. Typically, the information is in the form of data bits. The bus may have two states; high (or active) when a bit of a first type is being transmitted and low (or passive) when a bit of a second type is being transmitted. Each change of state takes place at a bit transition (from high to low, and low to high) that occurs coincident with a clock pulse at the transmitting node. A bit may be defined by its state and bit duration, where bit duration is determined by the number of clock pulses. A node transmitting a bit of a particular type will transmit a bit transition at the end of a bit (which becomes the beginning of the next bit), and will await a predetermined number of clock pulses before transmitting the next bit transition to define the end of that bit. For example, a bit of a particular type may be defined as having a high state and a duration of 64.+-.32 clock pulses, where clock pulses may be one microsecond apart. Each node may have its own clock 16 for providing clock pulses that may not be synchronized with clocks in other nodes. As discussed in the above-identified related application, that is incorporated by reference, a counter/decoder may provide a timing count. The counter/decoder may be reset to zero upon occurrence of an event such as receipt or transmission of a bit transition so that a count from the counter/decoder may be used to time bit duration.
When the communication system employs a non-destructive arbitration method, bits of a particular state are assigned either a high (dominant) or low (recessive) priority. Conflicts that may occur when two nodes are transmitting bits of different states on the bus are resolved in favor of a bit state that has a higher priority. The node transmitting the bit with the lower priority must recognize the conflict and stop transmitting, leaving the bus to the node that won the priority contest.
As will be appreciated, there may be periods of time when two nodes are transmitting bits of the same type at the same, or nearly the same, time (see, for example, FIG. 2). Each node will continue to transmit until it loses the priority contest because it does not recognize that there is a conflict (i.e., it senses that the bus is carrying the correct bit state).
When two or more nodes are transmitting bits of the same type, it is desirable to maintain synchronization of the clock pulses at the transmitting nodes--recall that each node has its own source of clock pulses--so that the bit durations remain within a defined tolerance (i.e., the bit transitions occur at the same time, or nearly so). Without synchronization, variation in the time bases (clocking frequency) and delay paths of the nodes may cause a divergence in the transmitted bit transitions that may, if allowed to grow, cause the communication system to malfunction. In some prior art systems, a common synchronization clock is provided to each of the nodes to synchronize the bit transitions on the bus. Such a technique generally adds equipment which is not necessary in the present invention.
Accordingly, it is an object of the present invention to provide a novel method and circuit for synchronizing multiple transmitting nodes in a multiplexed communication system that obviate these and other problems of the prior art.
It is a further object of the present invention to provide a novel method and circuit for synchronizing transmitting nodes in a multiplexed communication system in which synchronization depends only on received bit transitions.
It is another object of the present invention to provide a novel method and circuit for synchronizing bit transitions from transmitting nodes in which a node detecting a bit transition on the bus will be prevented from transmitting a bit transition for a predetermined period of time.
It is yet another object of the present invention to provide a novel method and circuit for preventing inadvertent bit transition transmission by blocking transmission of bit transitions from a node detecting a bit transition until detection of a predetermined number of clock pulses.